Pure Hardware Tetris on FPGA: Verilog Modular Design and Synthesis Verification

FPGA Resource Utilization Report — Post-Synthesis Resource Utilization in Vivado: Actual usage of LUTs, FFs, BRAMs, and other FPGA hardware resources

Implemented a complete Tetris game from scratch on FPGA using Verilog—including all seven standard tetrominoes (I/O/T/S/Z/J/L) with rotation, left/right movement, accelerated drop, line clearing with scoring, and real-time seven-segment display—all hardware logic, no CPU required.

1. Modular Hardware Architecture

The game logic was decomposed into five independent modules, each with a dedicated responsibility, coordinated through a Wrapper:

Keydebounce: Uses a counter to filter out mechanical key bounce, outputting stable key states
Bitmap (Grid Manager): Maintains a 32×16-bit grid, handling piece descent, landing detection and fixation, line clearing detection, and full-row scoring
BlockController (Tetromino Controller): Generates random pieces, responds to directional inputs, executes rotation (4×4 bit matrix rearrangement)
Segwrapper (Seven-Segment Driver): State machine polling 4-digit seven-segment display for dynamic score refreshing
Wrapper (Top-Level Scheduler): Manages game state (pause/speed), dispatches key events, generates descent tick signals

2. Key Design Details

Tetromino Rotation: Pure Bit Manipulation

Tetromino rotation is essentially a clockwise transposition of a 4×4 matrix. No lookup table was used—implemented purely with bit rearrangement:

Dual-Layer Grid: Dynamic Tetromino + Static Background

The Bitmap module maintains two grid layers: bitmap_l (the dynamic layer for the currently falling piece) and bitmap_h (the static layer for settled pieces). During display, the two layers are OR-combined; upon landing, bitmap_l is merged into bitmap_h:

Scoring System: Full-Row Detection

A 32-way parallel comparator detects the number of full rows, clearing and scoring in one pass—1 point for 1 line, 8 points for 4 lines (Tetris):

BlockController Simulation Waveform — BlockController Simulation: Timing verification of piece descent, rotation, and lateral movement—changes in cur_blk_row/col and correct rotation of cur_blk_data

Bitmap Grid Simulation Waveform — Bitmap Module Simulation: Waveform verification of real-time grid state updates, full-row detection, and line clearing logic

3. From Simulation to Synthesis

All five modules passed ModelSim functional simulation—key debouncing, piece movement and rotation, landing and fixation, line clearing and scoring, and seven-segment scanning display were all verified error-free. Subsequently, synthesis and place-and-route were completed in Vivado, and the bitstream file was successfully generated.

What makes this project special: no CPU, no operating system—all game logic (state machines, collision detection, scoring) is implemented entirely by pure combinational and sequential logic circuits. This represents a complete paradigm shift from software thinking to hardware thinking.

Tags: Portfolio

Author: 月儿

Date:2024年06月30日