月儿

1. Why Do This? If large language models taught AI to "speak," then Embodied AI teaches AI to "act" — not just to understand human language, but to execute actions in the physical world. The difficulty of this undertaking far exceeds imagination. Traditional robot control relies on

Building a cloud-edge-end three-layer decoupled multi-robot collaboration system from scratch — using large models for decision-making, edge computing for scheduling, and heterogeneous robots for pure execution.

1 引言 功率半导体器件是现代电能变换系统的核心，广泛应用于电动汽车、新能源发电、轨道交通、工业变频和航空航天等领域。随着第三代宽禁带（Wide Bandgap, WBG）半导体材料——碳化硅（SiC）和氮化镓（GaN）——的快速发展，功率器件的性能边界被不断拓展：更高的结温（200–300 °C）、更快的开关频率（>100 kHz）和更大的功率密度对封装技术提出了前所未有的挑战[1][2]。 功率模块封装需同时满足四大核心功能：芯片固定与保护、电气互联、热管理和环境隔离[3]。其中，封装互联技术直接决定了模块的寄生电感、散热效率和使用寿命，是整个封装体系中最关键的环节之一。传统硅基 IGBT 模块广泛采用的铝键合线与锡基焊料互联方案，在面对 SiC/GaN 器件时已显露出明显不足——键合线失效与焊层疲劳占据了模块失效原因的绝大部分[4][5]。 本文将系统综述功率电子封装互联技术的研究进展，涵盖传统键合线技术、

How do you squeeze a GPU-dependent SpatialLM 3D large model into an embedded board with only 10 TOPS of compute? This article documents the practice of PC encoding + RDK X5 inference in a separated deployment architecture.

From natural language to autonomous action — using a three-tier large model system to enable a quadruped robot dog to understand human commands, remember environmental information, and autonomously navigate to execute tasks.

背景 乘法器是数字IC中的核心算术单元，其性能直接影响整个系统的效率。在VLSI设计中，阵列乘法器因其规整的结构和简洁的实现方式被广泛应用。 这次我们基于0.18μm CMOS工艺、1.8V供电，完成了一款6×6位阵列乘法器的完整前后端设计——从晶体管级电路、标准单元库搭建，到版图绘制、DRC/LVS验证，再到后仿真性能评估，全流程走通。 设计亮点 1. 晶体管尺寸优化 通过参数扫描（NMOS宽度 0.4μm~2.0μm，20个线性步进），在面积×延迟的乘积曲线上找到了最优折中点。最终确定PMOS宽长比 (W/L)p = 2.5×(W/L)n，PMOS宽度统一 1.25μm，NMOS 0.5μm，沟道长度均为 0.18μm。 2.

From five-stage pipeline to Cache subsystem to VLIW dual-issue architecture—building a complete ARMv3 processor from scratch on FPGA, understanding modern CPU microarchitecture design.

From overfitting to 91% accuracy—using ResNet152 + Inception v3 + Xception three-model feature fusion, solving 120 dog breed fine-grained classification through four iterative rounds.

Using Silvaco ATLAS to simulate a complete PN junction diode from mesh definition to I-V characteristic extraction, understanding unidirectional conductivity from the physics level.

No CPU, no operating system—implementing Tetris on FPGA using pure Verilog hardware logic: rotation, collision detection, line clearing, and scoring for all seven tetrominoes with seven-segment display.

Encoding piece ranks with resistor values lets the circuit board act as referee—from schematic to PCB layout, a complete electronic military chess design that requires no third player.